Direct-sequence spread spectrum (DSSS) receivers can accurately compute their geographical position by receiving and analyzing the time of arrival (TOA) of different signals transmitted from reference transmitters. Signals transmitted by DSSS systems intentionally consume more signal bandwidth than what is actually required to transmit a data signal. One process of intentionally increasing the signal bandwidth is called “spreading”. Spreading a data signal over a greater bandwidth for transmission will result in a transmitted signal that has increased immunity to interference and jamming, prevents interception by unauthorized receivers (e.g., eavesdropping), and allows for transmission channel sharing.
One way of achieving spreading is by using DSSS modulation. In one implementation of DSSS modulation, a data signal is modulated with a bit sequence known as a pseudo-noise (PN) code. The PN code consists of a series of chips (e.g., pulses) having a shorter duration than the pulse duration of the data signal. By modulating the data signal with the series of pulses, a transmission signal is generated that has a bandwidth which is larger than the bandwidth of the data signal.
After a receiver receives the transmitted signal, the receiver must “de-spread” that signal in order to extract its data. One way to de-spread the signal is by using a correlator module to convolve samples of the signal with chips of a locally generated PN code. The result, known as a correlator function (CF), is read by a processor module of the receiver for further processing to compute the signal's TOA.
DSSS-based receivers have one or more “acquisition” correlator modules that de-spread the signals they receive, and identify the coarse timing of these signals. The receivers often have “tracking” correlator modules that de-spread the signals, and precisely identify the arrival time and other characteristics of the signals. Various challenges impact design and implementation of correlator modules: (1) different DSSS-based positioning systems may necessitate a different receiver correlator module since signal specifications for different systems can differ in terms of signal bandwidth, chipping rate and PN code length; (2) high clock rates used by correlator modules can result in high power consumption; (3) porting a correlator design to different architectures can be difficult since a correlator module is tightly coupled to a receiver's front-end modules; (4) correlator module implementations in ASIC's and FPGA's often require large logic and memory footprints; and (5) other challenges known in the art. Consideration of these and/or other challenges is needed when optimizing correlator modules. Different methods and systems for optimizing correlator modules are described in the disclosure that follows.